![When i was running simulation i get error in Xilinx Vivado as you can see in the picture. How can i fix it? : r/FPGA When i was running simulation i get error in Xilinx Vivado as you can see in the picture. How can i fix it? : r/FPGA](https://preview.redd.it/j0vy287mg8u91.png?auto=webp&s=8baf66f3780bb9a6dd6c60a995dc2762f0bc9954)
When i was running simulation i get error in Xilinx Vivado as you can see in the picture. How can i fix it? : r/FPGA
![Starting Active-HDL as Default Simulator in Xilinx Vivado 2017.4 or Later - Application Notes - Documentation - Resources - Support - Aldec Starting Active-HDL as Default Simulator in Xilinx Vivado 2017.4 or Later - Application Notes - Documentation - Resources - Support - Aldec](https://www.aldec.com/resources/articles/images/Starting_Active-HDL_as_the_Default_Simulator_in_Xilinx_Vivado_2017_04_fig1.png)
Starting Active-HDL as Default Simulator in Xilinx Vivado 2017.4 or Later - Application Notes - Documentation - Resources - Support - Aldec
66533 - Simulation - What files are needed to simulate Vivado IP in standalone Third party simulator?
![Compiling Xilinx Vivado Simulation Libraries for Active-HDL - Application Notes - Documentation - Resources - Support - Aldec Compiling Xilinx Vivado Simulation Libraries for Active-HDL - Application Notes - Documentation - Resources - Support - Aldec](https://www.aldec.com/resources/articles/images/Compiling_Vivado_Sim_Lib_in_AHDL_fig1.png)
Compiling Xilinx Vivado Simulation Libraries for Active-HDL - Application Notes - Documentation - Resources - Support - Aldec
![Starting Riviera-PRO as Default Simulator in Xilinx Vivado 2017.4 or Later - Application Notes - Documentation - Resources - Support - Aldec Starting Riviera-PRO as Default Simulator in Xilinx Vivado 2017.4 or Later - Application Notes - Documentation - Resources - Support - Aldec](https://www.aldec.com/resources/articles/images/Starting_Riviera-PRO_as_the_Default_Simulator_in_Xilinx_Vivado_2017_04_fig4.png)